1. Field of the Invention
The present invention generally concerns the dielectric composition of the several capacitors that are within a monolithic, buried-substrate, multiple capacitor, and particularly concerns the composition of the dielectric material of the monolithic multiple capacitor in its regions between its several buried capacitors.
The present invention still more particularly concerns the several buried capacitors of a buried-substrate, ceramic multiple capacitor which buried capacitors are isolated, one to the next, by a dual-dielectric-constant, three-layer-laminate, isolation layer that has and presents (i) a high dielectric constant (high K) at each of the two outer layers of the laminate, on either side of a low dielectric constant (low K) inner layer.
2. Description of the Prior Art
2.1 The Structure of Monolithic Multiple Buried-Substrate Capacitors
A monolithic buried-substrate, or multiple buried-substrate, multiple capacitor is sometimes identified with the two words "substrate" and "capacitor" reversed, and is sometimes called a Buried Capacitor Substrate, or BCS. Howsoever called, BCSs accord significant size reduction to microelectronic applications. A BCS integrates capacitors, resistors and traces together into a thin, multilayer, monolith which can be joined with integrated circuit ("IC") devices. Volumetric reductions over individual "chip" capacitor and/or resistor components of 50% to 75% are possible because the BCS both eliminates the air gaps between passive components and replaces the alumina substrate of traditional hybrids.
A BCS accords the freedom to mount one or more ICs directly onto itself (or perhaps even one on each side). The composite device so formed can then be attached to a ribbon lead, a larger hybrid, or a Multi Chip Module. The BCS is also compatible with flip chip IC designs, giving the most dense hybrids presently possible, circa 1995.
Substrate density and management of parasitic capacitances are the technological keys to BCS miniaturization. A BCS desirably uses the finest possible spacing for electrical connections around its edges (typically 0.020"), thus offering the greatest number of connections between an IC and the multiple capacitors that are buried within the BCS. Stray capacitance between these connections is preferably controlled by the unique castellation forming technique taught in the related U.S. Pat. No. 5,367,430 for a MONOLITHIC MULTIPLE CAPACITOR. Inside the BCS, multilayer technologies are used. Stray capacitance between these layers is preferably controlled by the use of high and low K dielectrics in combination, as is taught in U.S. Pat. No. 4,419,714 to Locke. These techniques combine to maintain parasitic capacitance at low levels, and to give low coupled noise, between internal capacitors.
Conductive traces and/or pads are typically placed only upon a "top", and sometimes also a "bottom", surface of the BCS. These conductive traces and/or pads are the basis by which electrical connections to the BCS are made. They have previously been formed by printing, particularly by screen printing and more particularly by silk screening.
Electrical connection to these various top and/or bottom surface printed conductive traces and pads can be made by soldering, various types of wire bonding, and/or flip-chip die attach. The BCS itself can be attached by soldering to either a larger hybrid, a Multi Chip Module, or a flexible ribbon cable. IC's and discrete components can be attached at one or another surfaces of the BCS. The conductive surface traces and pads are typically printed as 5 mil lines with 5 mil spacing, and in any pattern required to fit the application.
Electrical connection between the capacitors buried within the BCS and the printed circuit traces and pads upon its top and/or bottom surfaces are preferably made as a series of castellations along one or more sides of the BCS. The series of castellations provide selective electrical connection from the plates of capacitors within the body of the BCS to particular conductive traces and pads the top and/or bottom surfaces of the BCS. The castellations consist of metallized pads separated by 6 to 12 mil deep air gaps. A pitch 0.020 inches between castellations is possible while still retaining excellent solder reflow characteristics. These castellations are, again, the subject of related U.S. Pat. No. 5,367,430 for a MONOLITHIC MULTIPLE CAPACITOR.
A soldered connection to a castellation can provide a variety of electrical connections: 1) directly to the IC; 2) through a passive component and then to the IC; or 3) to the IC with a capacitor shunt to ground. In cases where an IC on each side of the BCS requires many I/O connections, a series of castellations can be made with 5 mil pads and 5 mil spaces.
BCS can be produced in a variety of sizes. A typical minimum size is 0.070 by 0.070 inches. The size of a BCS will usually be chosen based on capacitance values desired, the voltage rating, and internal space needed to control stray capacitance. Any sizes up to 1" by 1" and larger are possible, with maximum capacitance values near 10 uF. Again, the actual capacitance value achieved depends on the voltage rating required.
Because a BCS contain non-symmetric buried plates, variation in surface flatness can be expected. Production techniques allow three controls of this irregularity. A BCS can be made so that the top surface is flat and the bottom surface contains all the irregularity. A BCS can be made so that the bottom surface is flat and the top surface contains all the irregularity. Finally, a BCS can be made so that the irregularity is averaged on both sides, so that it is equally absorbed by the top and bottom surfaces.
Internal conductor traces can be used to connect castellations on side surface of the BCS to castellations upon another side surface of the BCS. Usually this is needed when internal capacitor arrangements make conventional layouts impossible, or to accommodate existing IC pad locations. The layer of connective traces can be put in at any level within the BCS, depending on what is optimal for reducing stray capacitance.
Various designs of the internal plates of each buried capacitor within a BCS are possible. Capacitance value depends on the active area of each capacitor and the number of layers used.
It is possible to design one or more capacitors adjacent to an internal ground plane. By changing the position of connecting tabs, almost any connection configuration can be achieved.
Shielded capacitors are created by having a series of capacitor plates which are surrounded by two ground planes. This shielding can occur above and below the capacitor or along the edge of the BCS.
Coupling capacitors can be designed using a stack of individual opposing plates. Again, capacitance value depends on the number of layers and the active area of each chip.
In a typical BCS, capacitors are stacked in different levels within the BCS; one or more capacitors are built on each level, and each capacitor tabs out to a different castellation. Typically one castellation will connect to all internal ground planes.
Stray capacitance between different internal capacitors within the BCS is controlled by varying the distance between the capacitors on the same level or by varying the layer thickness between levels.
BCS are commonly made from any of NPO, X7R, and Z5U dielectrics. For ease of designing a substrate, the dielectrics can be thought of as capacitance achieved per unit area, given a normalized dielectric thickness.
For an area 0.1 inches on a side, at a dielectric thickness of 0.001 inches, typical BCS capacitance values are as follows:
______________________________________ Capacitance per .01 inch Dielectric square @ 1.0 mil thick ______________________________________ NPO 312.7 pF X7R 7417 Pf ZSU 6,477 Pf ______________________________________
2.2 Previous Use of Multiple Dielectrics in Monolithic Buried-Substrate Ceramic Multiple Capacitors
It is previously know to make a monolithic buried-substrate ceramic multiple capacitor with, and from, multiple dielectrics that vary in dielectric constant (K). U.S. Pat. No. 4,882,650 to Maher, et al. for a MAGNESIUM TITANTATE CERAMIC AND DUAL DIELECTRIC SUBSTRATE USING SAME describes such a capacitor where each of multiple buried-substrate capacitors--formed from relatively thin alternating layers of a high dielectric constant (high-K) dielectric material and metallization--are separated, one capacitor to the next, by a relatively thick layer of a low dielectric constant (low-K) dielectric material. The purpose of the isolation layer of a material that, with its low dielectric constant (low-K), is different from the high dielectric constant (higher-K) material of the capacitors themselves, is to better reduce parasitic coupled capacitance, and thus any electrical cross-talk, between the buried capacitors.
Maher, et al, specifically discuss the interface between the high-K dielectric material of the capacitors and low-K dielectric material of the isolation layer between capacitors. Maher, et al, teach that it the materials on both sides of this interface must be physically and chemically compatible. Maher, et al, recommend barium titanate as the high-K material and magnesium zinc titanate as the low-K material. The average chemical composition of a "reaction band" between these differing layers is found to be Mg.sub.0.5 Ba.sub.0.25 Zn.sub.0.25 TiO.sub.3. This reaction band is formed when the two differing layers are co-sintered. The ratio of the dielectric constants of the two material preferably exceeds 100.
Applicants have no quarrel with the general principal of the Maher, et al, invention that large value buried-substrate capacitors made from high-K material should be isolated one to the next by intervening regions of low-K material. However, Maher et al. recognize that a physio-chemical reaction occurs at the boundary of the high-K and low-K layers during sintering. Applicants find this reaction--the "reaction band" of Maher, et al.--to be too close to, and excessively overlapping of, each outer (high-K) dielectric layer of a buried substrate capacitor to which the low-K dielectric, isolation, layer abuts. This is true of the ceramic multiple capacitor of the Maher, et al, design and all others where the outer layer of a buried-substrate capacitor is of a high-K material.
The reaction band "contaminates" the high-K dielectric and lowers its K. This undesirably serves to both (i) lower the capacitance of the (buried substrate) capacitor of which the ("contaminated") high-K dielectric is a layer, and (ii) increase leakage current. It would be desirable if this "contamination" of the buried substrate capacitor could be avoided while still realizing the advantages of an isolation zone, or layer, of low-K material, as is taught by Maher, et al.
Furthermore, it should be understood that a ceramic multiple capacitor is fused together in its several layers by the process of sintering. Whenever the different layers have differing thermal coefficients of expansion, than fracturing between layers is possible both (i) during sintering, and (ii) thereafter as the ceramic multiple capacitor is subjected to temperature changes and/or shock during use (such as in an electrical circuit). The thickness, as well as the thermal coefficient of expansion, of the sintered layers affects their stability. Progressing directly from relatively thin to relatively thick layers of different materials--which layers have different thermal coefficients of expansion as is the case in the Maher, et al. design--aggravates the potential for mechanical fracture induced by thermal stress.
Although thermally induced stress fractures are not a common failure mode in ceramic multiple capacitors--which are very robust and reliable components in the first place--if a ceramic multiple capacitor is rapidly cycled over a very broad temperature range--such as might happen, inter alia, in a spacecraft--and/or strongly shocked, then fracture failures can occur. Such fractures as do occur can generally be related, as would be expected, to the "weakest" boundaries between the many, many layers of the ceramic multiple capacitor. The boundaries occurring between the differing-thickness different-material layers (which are also of different dielectric constants) turn out to some of the weakest, and most failure prone, int eh multiple ceramic capacitor. Accordingly,, it would be useful if something could be done at or between the necessarily thin layers of a buried-substrate capacitor and the necessarily thick isolation layer (of low-K dielectric) so as to, among other things, improve the mechanical stability of this region to thermal stress and/or mechanical shock.
The present invention is directed to (i) reducing any negative impact on buried-substrate capacitors (made from layers, including outer layers, of high dielectric constant material) due to adjacent isolation layers of low dielectric constant material. The present invention is further directed to (ii) improving the mechanical stability between regions of high and low dielectric constant material in a ceramic multiple capacitor where multiple buried-substrate capacitors that are built (in part) from high dielectric constant (high-K) material are separated, one to the next, by regions of low dielectric constant (low-K) material.